//----------------------------------------------------------------------------- // port_grab.v Ver 0.4 2005.01.30 by K.Ishikawa //----------------------------------------------------------------------------- module port_grab(rst, clk, tx, rx, led, digit, segment); input rst; input clk; output tx; input rx; output [7:0] led; output [3:0] digit; output [7:0] segment; wire clk; wire tx; wire rx; reg [7:0] led; // // KCPSM3 Processor // wire [10:0] address; wire [17:0] instruction; wire [7:0] port_id; wire [7:0] out_port; reg [7:0] in_port; wire write_strobe; wire read_strobe; reg interrupt; wire interrupt_ack; kcpsm3 processor ( .address(address), .instruction(instruction), .port_id(port_id), .write_strobe(write_strobe), .out_port(out_port), .read_strobe(read_strobe), .in_port(in_port), .interrupt(interrupt), .interrupt_ack(interrupt_ack), .reset(rst), .clk(clk) ); // // Program ROM // mymon program_rom ( .address(address), .instruction(instruction), .clk(clk) ); // // Port Select // wire ps_uart_status; wire ps_uart_dat; wire ps_led_out; wire ps_segment_out; wire ps_ram_adr; wire ps_ram_dat; assign ps_uart_status = (port_id == 8'h 00); assign ps_uart_dat = (port_id == 8'h 01); assign ps_led_out = (port_id == 8'h 02); assign ps_segment_out_h = (port_id == 8'h 03); assign ps_segment_out_l = (port_id == 8'h 04); assign ps_ram_adr_h = (port_id == 8'h 05); assign ps_ram_adr_l = (port_id == 8'h 06); assign ps_ram_dat = (port_id == 8'h 07); // UART wire [7:0] uart_status_data; wire [7:0] uart_rx_data; reg read_from_uart; // 7seg LED reg [15:0] segment_data; // RAM reg [12:0] ram_address; wire [7:0] ram_data_out1; wire [7:0] ram_data_out2; wire [7:0] ram_data_out3; wire [7:0] ram_data_out4; wire cs_ram1; wire cs_ram2; wire cs_ram3; wire cs_ram4; assign cs_ram1 = (ram_address[12:11] == 2'b 00); assign cs_ram2 = (ram_address[12:11] == 2'b 01); assign cs_ram3 = (ram_address[12:11] == 2'b 10); assign cs_ram4 = (ram_address[12:11] == 2'b 11); always @(posedge clk) begin if ( ps_uart_status ) begin in_port <= uart_status_data; end else if ( ps_uart_dat ) begin in_port <= uart_rx_data; end else if ( ps_ram_adr_h ) begin in_port <= ram_address[12:8]; end else if ( ps_ram_adr_l ) begin in_port <= ram_address[7:0]; end else if ( ps_ram_dat ) begin if ( read_strobe ) begin ram_address <= ram_address + 1; end if ( cs_ram1 ) begin in_port <= ram_data_out1; end else if ( cs_ram2 ) begin in_port <= ram_data_out2; end else if ( cs_ram3 ) begin in_port <= ram_data_out3; end else if ( cs_ram4 ) begin in_port <= ram_data_out4; end end else begin in_port <= 8'b XXXXXXXX; end if ( write_strobe ) begin if( ps_led_out ) begin led <= out_port; end else if( ps_segment_out_h ) begin segment_data[15:8] <= out_port; end else if( ps_segment_out_l ) begin segment_data[7:0] <= out_port; end else if( ps_ram_adr_h ) begin ram_address[12:8] <= out_port; end else if( ps_ram_adr_l ) begin ram_address[7:0] <= out_port; end else if( ps_ram_dat ) begin ram_address <= ram_address + 1; end end read_from_uart <= read_strobe & ps_uart_dat; end // // 7seg LED // reg [15:0] count0; reg clk0; wire [3:0] sel_seg_dat; always @(posedge clk) begin if ( count0 == 0 ) begin clk0 <= ~clk0; end count0 <= count0 + 1; end seg_mux mux ( .DIN0(segment_data[15:12]), .DIN1(segment_data[11:8]), .DIN2(segment_data[7:4]), .DIN3(segment_data[3:0]), .CLK(clk0), .RST(rst), .DOUT(sel_seg_dat), .AN(digit) ); seg_decode decode ( .D(sel_seg_dat), .O(segment) ); // // UART // reg [9:0] baud_count; reg en_16_x_baud; wire tx_full; wire tx_half_full; wire rx_data_present; wire rx_full; wire rx_half_full; wire write_to_uart; assign uart_status_data = {3'b 000,rx_data_present,rx_full,rx_half_full,tx_full,tx_half_full}; assign write_to_uart = write_strobe & ps_uart_dat ; uart_tx transmit ( .data_in(out_port), .write_buffer(write_to_uart), .reset_buffer(rst), .en_16_x_baud(en_16_x_baud), .serial_out(tx), .buffer_full(tx_full), .buffer_half_full(tx_half_full), .clk(clk) ); uart_rx receive ( .serial_in(rx), .data_out(uart_rx_data), .read_buffer(read_from_uart), .reset_buffer(rst), .en_16_x_baud(en_16_x_baud), .buffer_data_present(rx_data_present), .buffer_full(rx_full), .buffer_half_full(rx_half_full), .clk(clk) ); // 153600Hz = 325 cycles at 50MHz always @(posedge clk) begin if (baud_count == 324) begin baud_count <= 1'b0; en_16_x_baud <= 1'b1; end else begin baud_count <= baud_count + 1; en_16_x_baud <= 1'b0; end end // // Block RAM // wire write_to_ram; wire parity1; wire parity2; wire parity3; wire parity4; assign write_to_ram = write_strobe & ps_ram_dat ; RAMB16_S9 RAMB16_S9_inst1 ( .DO(ram_data_out1), // 8-bit Data Output .DOP(parity1), .ADDR(ram_address[10:0]), // 11-bit Address Input .CLK(clk), // Clock .DI(out_port), // 8-bit Data Input .DIP (1'b0), .EN(cs_ram1), // RAM Enable Input .SSR(1'b0), // Synchronous Set/Reset Input .WE(write_to_ram) // Write Enable Input ); RAMB16_S9 RAMB16_S9_inst2 ( .DO(ram_data_out2), // 8-bit Data Output .DOP(parity2), .ADDR(ram_address[10:0]), // 11-bit Address Input .CLK(clk), // Clock .DI(out_port), // 8-bit Data Input .DIP (1'b0), .EN(cs_ram2), // RAM Enable Input .SSR(1'b0), // Synchronous Set/Reset Input .WE(write_to_ram) // Write Enable Input ); RAMB16_S9 RAMB16_S9_inst3 ( .DO(ram_data_out3), // 8-bit Data Output .DOP(parity3), .ADDR(ram_address[10:0]), // 11-bit Address Input .CLK(clk), // Clock .DI(out_port), // 8-bit Data Input .DIP (1'b0), .EN(cs_ram3), // RAM Enable Input .SSR(1'b0), // Synchronous Set/Reset Input .WE(write_to_ram) // Write Enable Input ); RAMB16_S9 RAMB16_S9_inst4 ( .DO(ram_data_out4), // 8-bit Data Output .DOP(parity4), .ADDR(ram_address[10:0]), // 11-bit Address Input .CLK(clk), // Clock .DI(out_port), // 8-bit Data Input .DIP (1'b0), .EN(cs_ram4), // RAM Enable Input .SSR(1'b0), // Synchronous Set/Reset Input .WE(write_to_ram) // Write Enable Input ); defparam RAMB16_S9_inst1.INIT = 1'h0; // Value of output RAM registers at startup defparam RAMB16_S9_inst1.SRVAL = 1'h0; // Ouput value upon SSR assertion defparam RAMB16_S9_inst1.WRITE_MODE = "WRITE_FIRST"; // WRITE_FIRST, READ_FIRST or NO_CHANGE defparam RAMB16_S9_inst2.INIT = 1'h0; // Value of output RAM registers at startup defparam RAMB16_S9_inst2.SRVAL = 1'h0; // Ouput value upon SSR assertion defparam RAMB16_S9_inst2.WRITE_MODE = "WRITE_FIRST"; // WRITE_FIRST, READ_FIRST or NO_CHANGE defparam RAMB16_S9_inst3.INIT = 1'h0; // Value of output RAM registers at startup defparam RAMB16_S9_inst3.SRVAL = 1'h0; // Ouput value upon SSR assertion defparam RAMB16_S9_inst3.WRITE_MODE = "WRITE_FIRST"; // WRITE_FIRST, READ_FIRST or NO_CHANGE defparam RAMB16_S9_inst4.INIT = 1'h0; // Value of output RAM registers at startup defparam RAMB16_S9_inst4.SRVAL = 1'h0; // Ouput value upon SSR assertion defparam RAMB16_S9_inst4.WRITE_MODE = "WRITE_FIRST"; // WRITE_FIRST, READ_FIRST or NO_CHANGE endmodule