module ram (clk24m, nWR, nRD, data, addr, led); input clk24m; input nWR; input nRD; inout [7:0] data; input [3:0] addr; output led; wire [7:0] out_data; wire ram_clk; wire wren; reg led; assign ram_clk = ~nWR | ~nRD; assign wren = ~nWR; ram_1port ram_1port0(.address(addr),.clock(ram_clk),.data(data),.wren(wren),.q(out_data)); assign data = ( nRD == 0 ) ? out_data : 8'hzz; endmodule